Speaker:   

Andrea Grimaldi

Affiliation:   

Polytechnic University of Bari, Italy

Title: 

Probabilistic Ising Machines: From Algorithms to Hardware

Date/Time:     

Tuesday- May 20, 2025

11:00 AM –  12:00 PM

Zoom link

https://argonne.zoomgov.com/j/1611401597?pwd=mphqouuBv8a17t0p5womEh4oNq4uQC.1

Abstract:

Ising machines are an unconventional computing paradigm that consists in determining the solution to hard computational problems by finding the energy minimum of an Ising model. Out of the possible implementations, probabilistic Ising machine rely on the p-bit, a bistable, tunable, stochastic unit [1] that can be easily implemented by physical systems like spintronic diodes [2]. To maximize the performance of such a system, it is necessary to work on three levels: the encoding, the energy minimization schedule, and the implementation.

The implementation of the Ising machine is what establishes the working speed, and thus the performance, of the system. Moreover, different hardware may impose limitations that also affect the compatible encodings and energy minimization schedules. Field-programmable gate arrays, for instance, allow for highly parallelizable computation, but require sparse graph topologies [3]. One of the technologies with the most potential for Ising machines is spintronics. Devices like magnetic tunnel junctions are intrinsically compatible with implementing an Ising spin in several ways. The parallel and anti-parallel state may encode the up and down state of the p-bit [5], or the phase of an oscillating magnetization of a spin-torque nano oscillator can be discretized using injection-locking to obtain the spin of an oscillatory Ising machine [5]. These systems are incredibly compact and energy efficient, on top of being characterized by high working speed and CMOS compatibility, making them excellent candidates for future applications geared towards the solution of computational problems in dedicated hardware.

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